In a conventional computer system, a memory controller is provided between a central processing unit (CPU) and a memory, and between an I/O bridge and the memory. A system address bus and a system data bus connect the CPU and the memory controller, and the I/O bridge and the memory controller. A memory address bus and a memory data bus connect the memory controller and the memory. When a failure occurs in the memory connected through the memory controller and the address line in the computer system, various methods can be performed to handle such a failure. Generally, when a failure occurs in a large-capacity memory in a server, the memory in which the failure occurs is isolated (memory degeneration), and the system is reactivated with other memories.
A memory failure includes that of a memory cell (memory element) mounted in the memory, and that of an address line connected to the memory. According to one known method, when permanent fault occurs in a memory cell, data is corrected according to ECC (Error Correcting Code) to avoid memory degeneration. According to another known method as that described in Japanese Laid-open Patent Publication No. 59-036394, when fixed data is written into a memory and failure occurs in one cell so that read-out data can only be “4”, address lines are switched so that the data written into the failed cell becomes “4”. Thus, the permanent fault of the memory cell can be avoided.
Other than that, Japanese Laid-open Patent Publication No. 55-028565 discloses a memory system that relieves a memory failure by mounting an auxiliary memory that substitutes a main memory. In this case, it becomes possible to avoid main memory degeneration because a memory failure is handled by switching an address line to the auxiliary memory both when a failure occurs in the memory cell of the main memory, and when a failure occurs in the address line of the main memory.
A problem occurs in the conventional technique of degenerating a failed memory in that, because the system is reactivated after memory degeneration, sometimes memory capacity becomes insufficient due to a significant decrease in memory capacity, and the system may not be able to be activated.
Another problem occurs in the conventional technique of avoiding permanent fault of a memory cell in that, although the processing for avoiding memory degeneration can be performed when a memory cell is failed, memory degeneration cannot be avoided when an address line is failed. In other words, a problem occurs in the conventional technique in that although memory degeneration can be avoided by correcting data or by switching address lines when a memory cell permanent fault occurs, a memory address line failure cannot be handled, and necessitating memory degeneration and system reactivation.
A problem occurs in the conventional technique of mounting an auxiliary memory in that memory degeneration can be avoided only if the auxiliary memory is mounted when a failure occurs in a memory cell of a main memory and when a failure occurs in an address line of the main memory, the cost of mounting the auxiliary memory increases, and memory degeneration cannot be avoided simply.
As can be seen, a problem occurs in all of the conventional techniques in that a significant decrease in memory capacity occurs due to memory degeneration when a failure occurs in a memory address line.